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\begin{document}
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\LARGE{\textsc{Computer Sciences Researcher}}\\
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			Jean-Fran\c{c}ois Le Tallec 	&& 153 Bvd Pierre Delmas\\
			24 Nov. 1981 in France && 06600 Antibes\\
			Marital Status: Single && France\\
			Nationality: French &&Tel. (Office): +33(0) 492 387 154\\
			 && Tel. (Cell): +33(0) 683 713 183\\
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			 && e-mail: Jean-Francois.Le\_Tallec@inria.fr
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	\section{Work Experiences}

	\begin{CV}
		\item[2007/2012] Ph.D. in Computer Sciences at INRIA laboratory/ScaleoChip Company\\
		Model extraction for Systems On Chip Design
		\item[2006/2007] 6 months research intern-ship at I3S laboratory (Sophia-Antipolis)\\
		Compilation and formal verification of SyncChart using polyhedra formalism
		\item[2005/2006] M.Sc. graduation project\\
		Boolean formula simplification using binary decision diagram formalism
	\end{CV}
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	\section{Education}

	\begin{CV}
		\item[2007-2012] Ph.D. in Computer Sciences
%		\\
%		\textbf{Dissertation title}: Model extraction for Systems On Chip Design
		\item[2006-2007] Research Master's Degree in Embedded Systems (Honours 2.2)
\begin{comment}
\iflong
		\\
		\textsl{
		General Training:
		\begin{itemize}
		\item Formal Method and Embedded Systems Reliability
		\item Reactive Synchronous Approach
		\item Different SoC's Applications Classes
		\item SystemC SoC modelling
		\item Multi-criteria SoC optimization
		\item Scheduling and schedulability analysis
		\item Digital Communications
		\item SoC conception \& SoC analysis methodology
		\item Physical attacks against crypto-processor
		\item Real-Time distributed Embedded Systems
		\end{itemize}
		}
\fi
\end{comment}
		\item[2005-2006] M.Sc. in Electronics, Electrotechnics \& Automatics (Honours 2.1)
		\item[2004-2005] B.Sc. in Electronics, Electrotechnics \& Automatics
		\item[2002-2004] Diploma of Higher Education in Material Sciences (spec Physics)
		\item[2000] A Levels in Sciences (spec Engineering Sciences)
	\end{CV}

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\section{Computing Skills}
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	\begin{CV}
%		\item[Computing]
%		\begin{CV}
			\item[HDL:] VHDL, Verilog
			\item[Imperative:] Assembler, C
			\item[Object:] C++, Java
			\item[Synchron:] Esterel, Lustre
			\item[Others:] \LaTeX, OpenOffice,\\ MS Office, Dreamweaver,\\ Eclipse, SVN
%		\end{CV}
	\end{CV}
\columnbreak
	\section{Other Experiences}
	\begin{CV}
		\item [Activity leader] (BAFA)
		\item [Barman]
		\item [Building worker]
		\item [Porter]
		\item [Private pre-A-level teacher]
		\item [Roofer]
		%\item []
	\end{CV}
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\begin{multicols}{2}
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\section{Languages}
	\begin{CV}
%		\item[Languages]
%		\begin{CV}
			\item[French:] Mother tongue
			\item[English:] Working knowledge
			\item[Italian:] Notion
%		\end{CV}
	\end{CV}

\columnbreak

	\section{Activities and Interests}
		\begin{CV}
			\item[Sports:] running, soccer, biking, tennis
			\item[Travel:] Italy, Spain, Irland, U.S.A. (C.A.)
			\item[Reading:] SF, Fantastique
		\end{CV}
\end{multicols}

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	\section{Publications and Conferences}
\iflong
	\begin{CV}
\newcommand{\etalchar}[1]{$^{#1}$}
\bibitem[LTDS11]{LETALLEC:2011:INRIA-00601843:1}
Jean-Fran{\c c}ois Le~Tallec and Robert De~Simone.
\newblock {SCIPX: a SystemC to IP-XACT extraction tool}.
\newblock In {\em {ESLsyn : Electronic System Level Synthesis Conference}}, San
  Diego, United States (California), June 2011.

\bibitem[LTDDS{\etalchar{+}}11]{LETALLEC:2011:INRIA-00601840:1}
Jean-Fran{\c c}ois Le~Tallec, Julien Deantoni, Robert De~Simone, Beno{\^\i}t
  Ferrero, Fr{\'e}d{\'e}ric Mallet, and Laurent Maillet-Contoz.
\newblock {Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design}.
\newblock In {\em {Workshop on Model Based Engineering for Embedded Systems
  Design (M-BED 2011)}}, Grenoble, France, March 2011.

\bibitem[LTD09]{LETALLEC:2009:INRIA-00494224:1}
Jean-Fran{\c c}ois Le~Tallec and Julien Deantoni.
\newblock {Toward a TLM to RTL refinement : a formal approach}.
\newblock In {\em {3rd Junior Researcher Workshop on Real-Time Computing
  (JRWRTC 2009)}}, Paris, France, October 2009.
	\end{CV}
\else
	On demand
\fi

	\section{Detailed Experiences}

	\begin{CV}
		\item[2007/2012] Ph.D. in Computer Sciences at INRIA laboratory/ScaleoChip Company\\
		\textbf{Model extraction for Systems On Chip Design}
\iflong		
		\\
%		ScaleoChip Supervisor: Bernard Plessier, Christine Dubois
%		\\
		\textsl{
		Location: INRIA Sophia-Antipolis, Team: AOSTE, Supervisor: Charles Andr\'{e}, Robert de Simone, Co-funding: PACA region, ScaleoChip
		\\	
		\textbf{Abstract:}
			The design of System on Chip mostly relies on SystemC/C++. This language allows architectural and behavioural descriptions at different abstraction levels. Others approaches consider automated assembly of components into actual or virtual platforms (IP-Xact format). Using Model Driven Engineering techniques is a new trend, which may benefit from UML profiles (especially MARTE). In this thesis, we study the modelling power of these approaches and the possible bridges between them. SystemC provides a great deal of examples while MARTE offers facilities in system modelling at different levels. So, we try to export SystemC designs to MARTE models. Beyond the mere conversion between formats, we propose an abstraction mechanism from SystemC code to models in IP-Xact formats. The IP-Xact description is then transformed into MARTE models with existing tools. We review related works and propose our solution leading to a dedicated tool called SCiPX (standing for SystemC to IP-Xact). In the second part of the thesis we apply the UML profile MARTE, its time model, and the associated language for specification of temporal constraints (CCSL) to specify interactions among components. A special attention is paid to protocol refinement. This study reveals a lack of CCSL for capturing the concept of priority. An improvement in the CCSL constraint solver is proposed to overcome this limitation.
		}
\fi
		\item[2006/2007] 6 months research intern-ship at I3S laboratory (Sophia-Antipolis)\\
		\textbf{Compilation and formal verification of SyncChart using polyhedra formalism}
\iflong
		\\	
		\textsl{
		\textbf{Abstract:} SyncChart is the graphical representation of the Esterel language. To verify program properties, existing compilers abstract constraints over integer and real variables to a boolean test. It induces a lose of information. This lose induces the detection of fake cycles and the rejection of a valid program. One way to tackle this problem is to use the polyhedra formalism to express such constraints and analyse reaching conditions in this formalism.
		}
\fi
		\item[2005/2006] M.Sc. graduation project\\
		\textbf{Boolean formula simplification using binary decision diagram formalism}
\iflong
		\\	
		\textsl{\textbf{Abstract}: Minimization problem for boolean formulas is known to be $NP^{NP}$. This humble project intended to prove optimality of a specific algorithm for a specific case . The algorithm was based on co-factors and the specific case was the three boolean variable formulas. The proof has been done by brute force enumeration.}
\fi

	\end{CV}

%	\section{Honors and Awards}

%	\begin{CV}
%		\item[2005-2007] Member of 
%	\end{CV}

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